1. Field of the Invention
The present invention relates to a Fast Fourier Transform (FFT) address generator, and more particularly to an FFT address generator that can generate addresses for a broad range of FFT sizes and can support hardware parallelism.
2. Description of the Related Art
The Discrete Fourier Transform (DFT) is the decomposition of a sampled signal in terms of sinusoidal components. If the signal is a function of time, such decomposition results in a frequency domain signal. The DFT is a fundamental digital signal processing algorithm used in many applications, including frequency domain processing and frequency analysis.
Because of its computational requirements, the DFT algorithm is usually not used for real time signal processing. Research has developed more efficient ways to compute the DFT by exploiting its symmetry and periodicity properties in order to significantly lower its computational requirements. The resulting algorithms are known collectively as Fast Fourier Transforms (FFTs). The FFT algorithm is based on the decomposition of the DFT computation. There are two decomposition approaches: decimation-in-time (DIT) and decimation-in-frequency (DIF).
The FFT is one of the most important algorithms in digital signal processing (DSP) applications. An FFT processor system mainly consists of two parts: the butterfly processor for arithmetic operation and an address generator for the generation of read/write addresses. The address generator provides addresses for the operation data for each butterfly calculation. As is known, the FFT butterfly computation operates on data in sets of r points, where r is called the radix. A P-point FFT uses P/r computation steps per computation stage for logrP stages. Each computation step requires two data values out of the set of data points. The computational result of one butterfly stage is the input data of the next butterfly stage.